1. Field of the Invention
The present invention relates to a system for detecting phase lock in a phase locked loop (PLL) which determines a phase of an oscillating frequency by detecting a phase of a frequency of a voltage controlled oscillator, and more particularly, to a detecting method which, based on a phase difference between an input reference frequency and an oscillating frequency, regulates a bandwidth in multiple steps to maintain the oscillating frequency exactly in phase with the input reference frequency. The present invention is based on Korean Application No. 44364/1996, which is incorporated herein by reference.
2. Description of the Related Art
Generally, a PLL system is a feedback loop that is used for extracting a base band signal from a frequency of a carrier wave. The general PLL system essentially includes a phase detector and a voltage controlled oscillator. The phase differences between the incoming carrier signal and an output from the voltage controlled oscillator are compared, and are used to control the frequency of the voltage controlled oscillator. As a result, the output voltage of the phase detector will have the same value as the base band of the incoming signal.
FIG. 1 is a block diagram of a general lock detecting system of a PLL. As illustrated in FIG. 1, a reference frequency (F.sub.ref) is received through an input terminal 104 of a phase detector 100. An oscillating frequency is fed back to the phase detector 100 which compares a phase difference between the reference frequency (F.sub.ref) and the oscillating frequency, and generates a phase differential signal. Based on the phase differential signal detected by the phase detector 100, a charging pump 101 controls an amount of current (I.sub.pump) input to a current input terminal 105 of the charging pump 101. A loop filter 102 generates a DC control voltage after filtering current provided by the charging pump 101. Based on the DC control voltage from the loop filter 102, a voltage controlled oscillator 103 determines an oscillating frequency which is then fed back to the phase detector 100. The oscillating frequency is ultimately output through an output terminal 106 of the voltage controlled oscillator 103.
The general lock detector of a PLL formed in the manner as described above receives a carrier wave which is changed to a reference frequency by input terminal 104, and an oscillating frequency of the voltage controlled oscillator 103. The phase detector 100 compares the phase difference between the two signals.
The following is a detailed description of the voltage controlled oscillator 103. After comparing the phases of the reference frequency and the oscillating frequency, as described above, if the phase of the reference frequency leads the phase of the oscillating frequency output by the voltage controlled oscillator 103, then an "Up" signal, represented as a logical "1", will be output by the phase detector 100 to the charging pump 101. On the other hand, if the phase of the reference frequency lags, then a "Down" signal, which is represented as a logical "0", will be output by the phase detector 100 to the charging pump 101. Based on the "up/down" (1/0) signal transmitted by the phase detector 100, the charging pump 101 controls the amount of current (I.sub.pump) which is received through the current input terminal 105. The controlled current is then provided to the loop filter 102.
More specifically, if the "Up" signal is received by the charging pump 101 from the phase detector 100, then the input current (I.sub.pump) will be provided by the charging pump 101 to the loop filter 102 unchanged. However, if the "Down" signal is received, then the input current (I.sub.pump) will be provided to the loop filter 102 after the input current level is reduced by a certain amount. The loop filter 102 filters the varied input current from the charging pump 101 and generates a corresponding DC control voltage to be sent to the voltage controlled oscillator 103.
Furthermore, the voltage controlled oscillator 103, using the DC control voltage, changes the oscillating frequency to be sent to the phase detector 100, and the oscillating frequency is ultimately output through output terminal 106. Consequently, since the oscillating frequency is controlled by the DC control voltage, a process of tracking starts in order to cause the reference frequency (R.sub.ref) and the oscillating frequency from the voltage controlled oscillator 103 to be exactly in phase.
In the general system, the locked condition, which occurs when the two frequencies mentioned above are exactly in phase, depends upon a bandwidth of the PLL system. The bandwidth can be controlled sequentially from the phase detector 100 to the voltage controlled oscillator 103, or can be controlled by an output current of the charging pump 101. However, if the PLL system is connected to multiple circuits, then the bandwidth (W) will have a relationship of W=I.sub.pump +L .
Therefore, when the general system contains a wide bandwidth due to a contained current in the charging pump 101, quick tracing is possible, but an ability to block frequency jittering diminishes. On the other hand, when the bandwidth is narrow, quick tracking is difficult, and a locked condition can be easily lost. Moreover, due to a large input current incurred by the charging pump 101, a large amount of voltage is consumed.